Системные файлы - bootloader для PIC18F25K80 v1.10 (06/01/2015)
; Catcatcat Electronics 2015
; питание контроллера 5 вольт
    LIST      P=PIC18F25K80          ; list directive to define processor
    #INCLUDE <P18F25K80.INC>         ; processor specific variable definitions
;   VREG Sleep Enable bit:
        CONFIG RETEN = OFF          ; Ultra low-power regulator is Disabled (Controlled by REGSLP bit)
;   LF-INTOSC Low-power Enable bit:
        CONFIG INTOSCSEL = LOW      ; LF-INTOSC in Low-power mode during Sleep
;   SOSC Power Selection and mode Configuration bits:
        CONFIG SOSCSEL = DIG        ; Digital (SCLKI) mode
;   Extended Instruction Set:
        CONFIG XINST = OFF          ; Disabled
;   Oscillator:
        CONFIG FOSC = HS2           ; HS oscillator (High power, 16 MHz - 25 MHz)
;   PLL x4 Enable bit:
        CONFIG PLLCFG = ON          ; Enabled
;   Fail-Safe Clock Monitor:
        CONFIG FCMEN = OFF          ; Disabled
;   Internal External Oscillator Switch Over Mode:
        CONFIG IESO = OFF           ; Disabled
;   Power Up Timer:
        CONFIG PWRTEN = ON          ; Enabled
;   Brown Out Detect:
        CONFIG BOREN = ON           ; Controlled with SBOREN bit
;   Brown-out Reset Voltage bits:
        CONFIG BORV = 0             ; 3.0V
;   BORMV Power level:
        CONFIG BORPWR = ZPBORMV     ; ZPBORMV instead of BORMV is selected
;   Watchdog Timer:
        CONFIG WDTEN = ON           ; WDT controlled by SWDTEN bit setting
;   Watchdog Postscaler:
        CONFIG WDTPS = 1048576      ; 1:1048576
;   ECAN Mux bit:
        CONFIG CANMX = PORTB        ; ECAN TX and RX pins are located on RB2 and RB3, respectively
;   MSSP address masking:
        CONFIG MSSPMSK = MSK5       ; 5 bit address masking mode
;   Master Clear Enable:
        CONFIG MCLRE = ON           ; MCLR Enabled, RE3 Disabled
;   Stack Overflow Reset:
        CONFIG STVREN = OFF         ; Disabled
;   Boot Block Size:
        CONFIG BBSIZ = BB1K         ; 1K word Boot Block size
;   Code Protect 00800-01FFF:
        CONFIG CP0 = ON             ; Enabled
;   Code Protect 02000-03FFF
        CONFIG CP1 = ON             ; Enabled
;   Code Protect 04000-05FFF:
        CONFIG CP2 = ON             ; Enabled
;   Code Protect 06000-07FFF:
        CONFIG CP3 = ON             ; Enabled
;   Code Protect Boot:
        CONFIG CPB = ON             ; Enabled
;   Data EE Read Protect:
        CONFIG CPD = ON              ; Enabled
;   Table Write Protect 00800-03FFF:
        CONFIG WRT0 = OFF           ; Disabled
;   Table Write Protect 04000-07FFF:
        CONFIG WRT1 = OFF           ; Disabled
;   Table Write Protect 08000-0BFFF:
        CONFIG WRT2 = OFF           ; Disabled
;   Table Write Protect 0C000-0FFFF:
        CONFIG WRT3 = OFF           ; Disabled
;   Config. Write Protect:
        CONFIG WRTC = OFF           ; Disabled
;   Table Write Protect Boot:
        CONFIG WRTB = OFF           ; Disabled
;   Data EE Write Protect:
        CONFIG WRTD = OFF           ; Disabled
;   Table Read Protect 00800-03FFF:
        CONFIG EBTR0 = OFF          ; Disabled
;   Table Read Protect 04000-07FFF:
        CONFIG EBTR1 = OFF          ; Disabled
;   Table Read Protect 08000-0BFFF:
        CONFIG EBTR2 = OFF          ; Disabled
;   Table Read Protect 0C000-0FFFF:
        CONFIG EBTR3 = OFF          ; Disabled
;   Table Read Protect Boot:
        CONFIG EBTRB = OFF          ; Disabled